The present invention relates to a method of fabricating a flash memory device and, more particularly, to a method of fabricating a flash memory device which can improve a hump characteristic of a transistor.
Semiconductor memory devices for storing data can be largely classified into volatile memory devices and non-volatile memory devices. The volatile memory devices lose stored data in the absence of electrical power, whereas non-volatile memory devices maintain stored data even though the supply of power is stopped.
The non-volatile memory device includes a flash memory device. A structure, including a tunnel dielectric layer, a floating gate, a dielectric layer and a control gate formed over an active region of a semiconductor substrate, has generally been adopted as a unit cell of the flash memory device.
In general, in forming the gate of the flash memory device, the control gate is formed of a stacked structure of a polysilicon layer and a tungsten silicide (WSix) layer. In a process of forming the tungsten silicide layer, surface roughness is generated, causing a step. The surface roughness generated in the process of forming the tungsten silicide layer is transferred to a hard mask layer, which is subsequently formed on the tungsten silicide layer, and also to a Self-Aligned Contact (SAC) nitride layer formed on the gate surface in order to protect the gate at the time of a polishing process of a pre-metal dielectric layer for forming a contact plug after the gate is etched. Consequently, a step is generated in regions in which the surface roughness has occurred.
Due to this, in the polishing process of the pre-metal dielectric layer for forming the contact plug, the SAC nitride layer formed in the region in which the surface roughness has occurred is lost. Thus, during a subsequent process, impurities such as hydrogen (H2) are infiltrated into the bottom of the gate through the lost portion of the SAC nitride layer, degrading the tunnel dielectric layer. Accordingly, a transistor hump phenomenon, such as that the leakage current is generated in the transistor, are generated due to the degradation of the tunnel dielectric layer. The hump phenomenon has an effect on the transistor, causing well stress fail and therefore reducing the yield.